We Hid All the Labels. The Algorithm Found the Carry Chain. Here Is What That Proves -- and Does Not.
We ran IRDME on a 4-bit ripple carry adder with all gate labels replaced by neutral IDs. 4/4 hypotheses confirmed: the carry-chain gates (G_12=cout_1, G_20=cout_0, G_21=cout_2) were the top structural hubs. Honest scope: a ripple-carry adder has a linear carry chain that is a trivially recoverable structural backbone -- any centrality method finds it. This experiment validates the IRDME pipeline on hardware and establishes the starting point, but does not demonstrate a novel inference capability. The harder test (c6288 32-bit multiplier, FPL vs betweenness baseline) is next.
The Setup
A 4-bit ripple carry adder has 29 nodes: 9 primary inputs (A0-A3, B0-B3, Cin), 4 XOR gates, 8 AND gates, 3 carry-propagation gates (cout_0, cout_1, cout_2), and 5 outputs (Sum_0-3, cout_3).
- For this experiment, we replaced every node name with a neutral ID. G_00 through G_28 -- shuffled, with no pattern that could reveal which ID corresponds to which gate. The dataset file contains no gate types, no function descriptions, no semantic labels of any kind. Just:
- : directed physical connections between gates (40 edges)
- : pairwise Pearson correlations computed by simulating all 512 input combinations (48 edges above |r| > 0.40)
We ran IRDME on this blind dataset. Before seeing any results, we pre-registered four hypotheses.
Pre-Registration
What IRDME Found
All 4 hypotheses confirmed.
h1 -- FPL holds in blind circuit: CONFIRMED. r = 0.5117, p = 0.002.
h2 -- G_20 top-5 in structural_wiring: CONFIRMED. Rank 5.
h3 -- G_20 top-3 in state_correlation: CONFIRMED. Rank 2.
h4 -- G_12 rank 1 in state_correlation: CONFIRMED. G_12 is also the most central node by betweenness.
The Reveal
The state_correlation top-3 (G_12, G_20, G_21) are the three carry-chain propagation gates. G_12 (cout_1) is the single most important node by every measure. 9 input nodes and 5 output nodes are also correctly identified from in-degree=0 and out-degree=0 respectively.
Honest Scope -- What This Does and Does Not Prove
A reviewer raised the following critique after this post was published, and it is correct.
What this experiment does NOT demonstrate:
A 4-bit ripple-carry adder has a linear carry chain (cout_0 -> cout_1 -> cout_2 -> cout_3) that is a structural backbone by construction. Any algorithm that tracks state propagation, measures correlation across simulation states, or computes any centrality metric will rank these nodes highest. PageRank, betweenness centrality, degree centrality, random walk diffusion -- all would find the same result.
Renaming nodes G_00 to G_28 does not anonymize the graph in an information-theoretic sense. The topology directly encodes the carry chain through degree distribution and path structure. The black-box framing was overconfident.
This experiment demonstrates: (1) the IRDME pipeline processes digital circuits correctly, (2) FPL holds in hardware (replicating H_LOGIC_DIGITAL_v1 and H_LOGIC_F3_ISCAS85), (3) the circuit extraction and blind-labeling workflow is reproducible. It does NOT demonstrate that IRDME recovers something that simpler methods cannot.
What a genuine strong result would require:
The scientifically interesting claim is: FPL's cross-layer signal (nodes that are hubs in BOTH structural_wiring AND state_correlation) identifies functional roles more accurately than single-layer betweenness in circuits where structural and functional critical paths diverge.
A ripple-carry adder has no such divergence -- carry gates are critical in both layers simultaneously.
The correct test uses a circuit where some nodes are structurally prominent (high betweenness in structural_wiring) but NOT operationally central (low in state_correlation), and other nodes are the reverse. A 32-bit Wallace tree multiplier (ISCAS85 c6288) or a single-error-correcting circuit (c1908) provides this. The partial-product generation tree has high structural degree but the final carry-propagate adder is the operational bottleneck -- these are different node sets.
That experiment is H_LOGIC_ISCAS_BASELINE_v1 and is the correct next step.
What This Result Is Good For
This experiment is valid as: a pipeline integration test, a replication of the FPL-in-hardware result in a pre-registered blind setting, and a demonstration that the structural class separation (inputs/outputs/carry-gates/XOR-gates) is visible from topology. It is part of the scaling chain that motivates the harder test.
The TAL (Topology-as-Logic) claim -- that structural topology recovers functional roles -- requires the harder circuit to be compelling. This experiment is the validated starting point, not the proof.
Pre-Registration Record
Reproducibility
This result was pre-registered before analysis. SHA-256 hash: 3ff502c3aedb9686130556b5455edee142cc5f1c39238423e9b7a6c5c84ca1e3
Verify at github.com/vladi160/preregistrations