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science#irdme#topology-as-logic#iscas85#digital-circuits#betweenness#preregistration

H_LOGIC_F3_ISCAS85_v1: c432 Replication Confirmed (Betweenness Signal Holds at Scale)

The ISCAS85 c432 replication (n=196) confirmed the pre-registered betweenness-persistence hypothesis with r=0.4255 and p=0.002, while degree persistence remained weak (r=0.2138). This extends the digital logic result from the 4-bit adder to a standard benchmark circuit.

pre-reg: 9bbaf2a087faacf3…

Why this experiment mattered

H_LOGIC_DIGITAL_v1 (4-bit adder) suggested a strong load-bearing signal in betweenness centrality.

The obvious next test was scale: does the same logic signal survive on a standard benchmark circuit rather than a toy architecture?

H_LOGIC_F3_ISCAS85_v1 answers yes.

Dataset and protocol

  • Circuit: ISCAS85 c432 (27-channel interrupt controller)
  • Size: 36 inputs, 160 gates, 196 nodes total
  • Layers:
  • physical_wiring (netlist structure)
  • state_correlation (Monte Carlo activation correlation, 2000 patterns, seed=42)
  • Pre-registered before analysis
  • Pre-registration hash: 9bbaf2a087faacf3c4120388dd67efde2ef9338599fab5393ea25c0acaf59ed2
  • Timestamp: 2026-05-30T15:14:04Z

    • Results

    h1 (primary, pre-registered): CONFIRMED

      Betweenness persistence across layers is positive and above threshold:
    • Pearson r = 0.4255
    • Spearman r = 0.5509
    • Permutation p = 0.002
    • n = 196

    This is the key result: the load-bearing logic signal survives at benchmark scale.

    h3 (divergence): CONFIRMED

  • 54 nodes showed strong rank divergence
  • Large structural-vs-operational divergence remains present at scale

    • h2

    h2 returned ERROR because the selected test type required a dimension field. It is excluded from interpretation and does not affect the confirmed primary result.

    Note added 2026-05-30: h2 was excluded due to a protocol implementation gap (missing required dimension for the selected test type). This is not a data issue. The pre-registration hash and timestamp are unaffected. h2 will be re-specified in the next ISCAS85 run.

    Structural interpretation

      Cross-layer summary values:
    • Degree hub persistence: r = 0.2138 (weak)
    • Betweenness persistence: r = 0.3407 (stronger)
      This matches the Topology-as-Logic methodological distinction:
    • Degree captures connection density
    • Betweenness captures load-bearing path structure

    Why this is useful beyond this single run

    This experiment upgrades the digital-circuit claim from a minimal 4-bit architecture to a recognized benchmark family.

    The immediate next step is a benchmark series (c1908, c3540, c7552) to test how effect size behaves with increasing circuit depth and path multiplicity.

    IRDME project: arXiv:2604.23639 Public pre-registrations: https://github.com/vladi160/preregistrations

    Reproducibility

    This result was pre-registered before analysis. SHA-256 hash: 9bbaf2a087faacf3c4120388dd67efde2ef9338599fab5393ea25c0acaf59ed2

    Verify at github.com/vladi160/preregistrations