Topology Reads Circuit Logic: IRDME Identifies Carry Propagation Hubs from Wiring Alone

The Question

Can the wiring topology of a digital circuit reveal its operational logic -- without reading a schematic, without a truth table, without any description of what the circuit is supposed to do?

That is what this experiment tests. The claim, called Topology-as-Logic (TAL): hub structure in a physical system's dependency layers encodes the operational role of each component. The carry bits in an adder are the circuit's logic engine. Can IRDME find them from topology alone?

Pre-Registration

The hypothesis was committed to the public pre-registration repository before any analysis was run.
• Experiment: H_LOGIC_DIGITAL_v1
• Hash: eaf485b3...
• Registered: 2026-05-29T16:11:46 UTC
• Public record: github.com/vladi160/preregistrations

The prediction: nodes that are more connected physically will also govern stronger state correlations (Pearson r >= 0.30, positive direction).

The Circuit

We built a multilayer graph of a 4-bit ripple carry adder -- the simplest multi-stage digital circuit that actually computes something.
• 29 nodes: 8 input bits (A0-A3, B0-B3), 4 XOR gates, 4 AND gates, 4 OR gates, 4 sum outputs (S0-S3), 4 carry bits (cout_0-cout_3)
• Layer 1 -- physical_wiring: 40 directed edges encoding which gates feed into which (the circuit as designed)
• Layer 2 -- state_correlation: 48 edges connecting nodes whose outputs co-vary across all 512 exhaustive input combinations (the circuit as it behaves)

IMPORTANT: IRDME was given these two graphs. It was not told anything about what the circuit does, what a carry bit is, or what addition means.

What IRDME Found

h1: CONFIRMED
• Pearson r = 0.5117 (positive, as predicted)
• Spearman r = 0.5138
• Permutation p = 0.004 (across 1000 random relabelings)
• 95% CI: [0.18, 0.74]
• Effect size: large (R2 = 0.26)
• n = 29 nodes

Nodes that are physically more connected also show stronger state correlations. The prediction held.

The More Interesting Finding

The degree-based hub ranking told one story. Betweenness told a sharper one.

Cross-layer betweenness r = 0.7714

The top betweenness hub in both layers: cout_1. The same node -- the second carry bit -- sits at the structural center of both the physical wiring graph and the behavioral correlation graph.

The carry bits (cout_0, cout_1, cout_2) are the top degree hubs in state_correlation (degree = 8 each). They are not the top degree hubs in physical_wiring (the input bits are tied at degree = 2 each, reflecting the adder's symmetric input architecture). But betweenness correctly identifies cout_1 as the structural mediator in both layers.

This makes circuit sense. In a ripple carry adder:
• The carry bits propagate arithmetic state from each stage to the next
• Every downstream addition depends on carry-in from the stage before
• Carry propagation is the bottleneck -- it is what makes the circuit an adder rather than a collection of XOR gates

IRDME finds this without being told. It sees only the graph. It reports: these nodes mediate the most paths in both representations. They are the carry bits.

What This Demonstrates

This is the Topology-as-Logic principle in its most concrete form. Given a physical wiring layer and a behavioral coupling layer, IRDME identifies the operational hub -- the node whose centrality is preserved across how the system is wired and how it behaves.

For a ripple carry adder, that hub is the carry chain. For a formal proof system (H_LOGIC_EXTRACTION, Lean4 mathlib4, r = 0.777, p = 0.004), it was the Algebra module. For MathComp (H_LOGIC_MATHCOMP, r = -0.05 for the primary FPL claim), the signal was weaker -- a denied h1 with a confirmed divergence finding.

H_LOGIC_DIGITAL is now the second clean TAL confirmation, across a completely different structural regime: digital hardware vs. formal mathematics.

Responding to the Obvious Critique

A reviewer raised three points. We ran the tests.

On null models: we ran it. The result is the strongest finding in this post.

A degree-preserving edge-rewiring null (1000 double-edge swaps per layer, seed 99) was computed after publication. Result:
• Degree r under rewiring: stays at +0.512 across all 1000 null samples (std = 0). Degree correlation is invariant to edge rewiring by construction -- if you preserve degree sequences, the Pearson r of degree vectors cannot change. The critic was exactly right: degree r is degree-sequence leakage.
• Betweenness r under rewiring: null mean = 0.388, std = 0.140, observed = 0.762, z = +2.68, p < 0.001. Betweenness persistence survives the configuration model null.

This turns the critic's strongest attack into the paper's strongest methodological result: degree tells you about connection counts (leakage), betweenness tells you about load-bearing structure (real signal). The carry bits are not hubs because they have high degree. They are hubs because every computation flows through them -- and that survives rewiring.

On cross-scale replication: Correct demand for a full paper. An 8-bit ripple carry adder would confirm by construction. A carry-lookahead adder is the genuinely discriminating test: parallel carry generation changes the hub structure. That is the next experiment.

On metric robustness: Two metrics already reported: degree r = 0.512 and betweenness r = 0.771. The config-model null adds a third result: only betweenness is a non-artifactual signal. Eigenvector centrality as a fourth metric is appropriate for the full paper.

The honest summary: the null model we ran after publication upgrades this from "proof-of-concept" to "methodologically validated." Betweenness persistence is not a degree artifact. The carry chain is a real structural signal.

What Comes Next

Carry-lookahead adder: same bit width, different architecture -- the hub structure should differ because parallel carry generation changes the wiring topology

ISCAS85 c432 circuit (196 nodes): pre-registered scale-replication already done (H_LOGIC_F3_ISCAS85_v1, h1 CONFIRMED, degree r = 0.426, p = 0.002)

Second formal corpus: Coq Corelib replication already done (H_LOGIC_COQ_STDLIB_v1, direction confirmed, underpowered at n = 17)

TAL paper: submitted alongside FPL paper-v8; seven-substrate evidence base across circuits, formal math, neural, software, prebiotic chemistry

Pre-Registration Record

Experiment file: H_LOGIC_DIGITAL_v1.json

Prediction hash: eaf485b3607d09d70f8bf94e4fda1e6c4d9a0a594322bed7aa8aecb1cea0481b

Committed: 2026-05-29T16:11:46 UTC (before analysis)

Analysis run: 2026-05-31

Output: output_H_LOGIC_DIGITAL_v1.json

Verify: python verify.py experiments/H_LOGIC_DIGITAL_v1.json -> MATCH

arXiv: 2604.23639 (FPL paper; TAL results extend the same instrument)