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Each post is a discovery. IRDME is the method — the finding is the story. All results link to their pre-registered hash.

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hardware#topology-as-logic#betweenness#FPL#ISCAS85#pre-registered#TAL#baseline2604.23639

Three Methods. Three Different Most-Important Nodes. Same Circuit.

We ran FPL cross-layer analysis, structural betweenness, and state correlation on ISCAS85 c6288 (16x16-bit Wallace tree multiplier, 2448 nodes). All three identified different nodes as most important. Betweenness: node 6207 (internal final-adder gate). State correlation: node 256 (A[15], MSB -- betweenness=0.00). Structural degree: node 1 (tied with 31 others). Node 256 has state_correlation degree=81 but betweenness=0 -- invisible to single-layer structural analysis. FPL holds strongly (r=0.5004, p=0.002, z=+23.22 above null). 1022/2448 nodes (42%) are cross-layer divergers. Directly answers the critique of H_LOGIC_BLACKBOX_v1. Pre-registered. 4/4 confirmed.

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hardware#topology-as-logic#black-box#digital-circuit#carry-chain#FPL#pre-registered#TAL2604.23639

We Hid All the Labels. The Algorithm Found the Carry Chain. Here Is What That Proves -- and Does Not.

We ran IRDME on a 4-bit ripple carry adder with all gate labels replaced by neutral IDs. 4/4 hypotheses confirmed: the carry-chain gates (G_12=cout_1, G_20=cout_0, G_21=cout_2) were the top structural hubs. Honest scope: a ripple-carry adder has a linear carry chain that is a trivially recoverable structural backbone -- any centrality method finds it. This experiment validates the IRDME pipeline on hardware and establishes the starting point, but does not demonstrate a novel inference capability. The harder test (c6288 32-bit multiplier, FPL vs betweenness baseline) is next.

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